In present telecommunications and digital audio systems, digital-to-analog converters (DACs) having higher resolution, as well as requiring less surface area on an integrated circuit are needed. Linearity errors that reduce resolution and accuracy in an analog output signal may be caused by processing variations and component value mismatching. To achieve higher resolution, relatively large surface area, and/or special equipment, such as laser trimmers, may be required. In addition, various calibration techniques have been used to improve linearity of the analog output signal. One calibration technique used with current-mode DACs is disclosed in "A Self-Calibration Technique For Monolithic High-Resolution D/A Converters", by Groeneveld et al., IEEE Journal of Solid-State Circuits, Vol. 24, No. 6, December 1989, pp. 1517-22, and involves calibrating each current source element in the converter independently. A current-mode DAC uses current instead of voltage to represent an analog signal. The DAC is implemented using 2.sup.K +1 current source elements, where K represents the number of bits received by the DAC. During every clock cycle, 2.sup.K of the elements are switched to the output or to ground depending on the DAC input code. The one remaining current source element is calibrated relative to a reference current source. During each clock cycle, a different current source element is calibrated until eventually all of the elements have been calibrated. The calibration cycle then repeats.
A problem with the calibrated current source implementation is that it may require a very large number of current source elements to implement a high resolution DAC. For example, a 12-bit DAC requires 2.sup.12, or 4096 elements. To reduce the number of current source elements in a DAC, one common technique is to use two smaller DACs together with a divide-by-2.sup.N attenuator. N represents the number of bits in each of the two DACs. In this manner, a high resolution DAC can be implemented using two low resolution DACs. For example, a 12-bit DAC can be implemented using two 6-bit DACs. Each 6-bit DAC requires 2.sup.6, or 64 current source elements. Thus, a 12-bit DAC can be simplified from 4096 elements to 128 elements. However, the divide-by-2.sup.N attenuator should be accurate in order in order to maintain high-linearity in the DAC. A typical divide-by-2.sup.N attenuator is implemented using a current divider in a current-mode DAC, however, the accuracy of the current divider can be degraded by device mismatch. This can be a significant problem in high resolution DACs requiring high linearity.